Comparison of time and frequency domain interpolation implementations for MB-OFDM UWB transmitters

This paper investigates the effect of time-domain (TD) and frequency-domain (FD) interpolation on the performance of a Multi-Band (MB) Orthogonal Frequency Division Multiplexing (OFDM) Ultra-Wideband (UWB) system. We introduce a FD interpolator implemented by a radix-8 512-point IFFT architecture for applications on MB-OFDM UWB transmitters. For the specific application where the interpolation factor is fixed to four, the FD interpolator outperforms the TD interpolator implemented with digital low-pass FIR filters in terms of computational complexity. On the other hand simulation results show that FD implementation degrades the overall system performance for certain UWB channels

Comparison of time and frequency domain interpolation implementations for MB-OFDM UWB transmitters

This paper investigates the effect of time-domain (TD) and frequency-domain (FD) interpolation on the performance of a Multi-Band (MB) Orthogonal Frequency Division Multiplexing (OFDM) Ultra-Wideband (UWB) system. We introduce a FD interpolator implemented by a radix-8 512-point IFFT architecture for applications on MB-OFDM UWB transmitters. For the specific application where the interpolation factor is fixed to four, the FD interpolator outperforms the TD interpolator implemented with digital low-pass FIR filters in terms of computational complexity. On the other hand simulation results show that FD implementation degrades the overall system performance for certain UWB channels

Performance Analysis of Coherent and Noncoherent Modulation under I/Q Imbalance

In-phase/quadrature-phase Imbalance (IQI) is considered a major performance-limiting impairment in direct-conversion transceivers. Its effects become even more pronounced at higher carrier frequencies such as the millimeter-wave frequency bands being considered for 5G systems. In this paper, we quantify the effects of IQI on the performance of different modulation schemes under multipath fading channels. This is realized by developing a general framework for the symbol error rate (SER) analysis of coherent phase shift keying, noncoherent differential phase shift keying and noncoherent frequency shift keying under IQI effects. In this context, the moment generating function of the signal-to-interference-plus-noise-ratio is first derived for both single-carrier and multi-carrier systems suffering from transmitter (TX) IQI only, receiver (RX) IQI only and joint TX/RX IQI. Capitalizing on this, we derive analytic expressions for the SER of the different modulation schemes. These expressions are corroborated by comparisons with corresponding results from computer simulations and they provide insights into the dependence of IQI on the system parameters. We demonstrate that the effects of IQI differ considerably depending on the considered system as some cases of single-carrier transmission appear robust to IQI, whereas multi-carrier systems experiencing IQI at the RX require compensation in order to achieve a reliable communication link

Number Systems for Deep Neural Network Architectures: A Survey

Deep neural networks (DNNs) have become an enabling component for a myriad of artificial intelligence applications. DNNs have shown sometimes superior performance, even compared to humans, in cases such as self-driving, health applications, etc. Because of their computational complexity, deploying DNNs in resource-constrained devices still faces many challenges related to computing complexity, energy efficiency, latency, and cost. To this end, several research directions are being pursued by both academia and industry to accelerate and efficiently implement DNNs. One important direction is determining the appropriate data representation for the massive amount of data involved in DNN processing. Using conventional number systems has been found to be sub-optimal for DNNs. Alternatively, a great body of research focuses on exploring suitable number systems. This article aims to provide a comprehensive survey and discussion about alternative number systems for more efficient representations of DNN data. Various number systems (conventional/unconventional) exploited for DNNs are discussed. The impact of these number systems on the performance and hardware design of DNNs is considered. In addition, this paper highlights the challenges associated with each number system and various solutions that are proposed for addressing them. The reader will be able to understand the importance of an efficient number system for DNN, learn about the widely used number systems for DNN, understand the trade-offs between various number systems, and consider various design aspects that affect the impact of number systems on DNN performance. In addition, the recent trends and related research opportunities will be highlightedComment: 28 page

Area-throughput trade-offs for SHA-1 and SHA-256 hash functions’ pipelined designs

High-throughput designs of hash functions are strongly demanded due to the need for security in every transmitted packet of worldwide e-transactions. Thus, optimized and non-optimized pipelined architectures have been proposed raising, however, important questions. Which is the optimum number of the pipeline stages? Is it worth to develop optimized designs or could the same results be achieved by increasing only the pipeline stages of the non-optimized designs? The paper answers the above questions studying extensively many pipelined architectures of SHA-1 and SHA-256 hashes, implemented in FPGAs, in terms of throughput/area (T/A) factor. Also, guides for developing efficient security schemes designs are provided. Read More: https://www.worldscientific.com/doi/abs/10.1142/S021812661650032

Arithmetic circuits for DSP applications

Arithmetic Circuits for DSP Applications is a complete resource on arithmetic circuits for digital signal processing (DSP). It covers the key concepts, designs and developments of different types of arithmetic circuits, which can be used for improving the efficiency of implementation of a multitude of DSP applications. Each chapter includes various applications of the respective class of arithmetic circuits along with information on the future scope of research. Written for students, engineers, and researchers in electrical and computer engineering, this comprehensive text offers a clear understanding of different types of arithmetic circuits used for digital signal processing applications. The text includes contributions from noted researchers on a wide range of topics, including a review o circuits used in implementing basic operations like additions and multiplications; distributed arithmetic as a technique for the multiplier-less implementation of inner products for DSP applications; discussions on look up table-based techniques and their key applications; CORDIC circuits for calculation of trigonometric, hyperbolic and logarithmic functions; real and complex multiplications, division, and square-root; solution of linear systems; eigenvalue estimation; singular value decomposition; QR factorization and many other functions through the use of simple shift-add operations; and much more. This book serves as a comprehensive resource, which describes the arithmetic circuits as fundamental building blocks for state-of-the-art DSP and reviews in - depth the scope of their applications

A reliable and energy efficient IoT data transmission scheme for smart cities based on redundant residue based error correction coding

Cities today face multifarious challenges, including environmental sustainability, and low carbon solutions. Given these trends, it is critical to understand how information and communication technology (ICT) can benefit the future of city-planning process. Internet of Things (IoT) is a futuristic communication concept integrating plethora of interconnected heterogeneous objects forming a large scale smart city system, that is, it can communicate and control other objects over a global network. Hence, devising a fault tolerant mechanism is very important because of construction and deployment characteristics of these smart low powered sensing devices. In this paper, we propose a fault detection and error correction scheme based on redundant residue arithmetic, which provides a low complexity, delay tolerant and energy-efficient data transmission solution. By comparing the proposed method with existing solution in perceived packet loss rate and expected delivery latency, we show advantages of the proposed solution in improving data transmission quality

An RNS implementation of an Fp elliptic curve point multiplier

Elliptic curve point multiplication is considered to be the most significant operation in all elliptic curve cryptography systems, as it forms the basis of the elliptic curve discrete logarithm problem. Designs for elliptic curve cryptography point multiplication are area demanding and time consuming. Thus, the efficient realization of point multiplication is of fundamental importance for the performance of an elliptic curve system. In this paper, a hardware architecture of an elliptic curve point multiplier is proposed that exploits the intrinsic parallelism of the residue number system (RNS), in order to speed up the elliptic curve point calculations and minimize the area complexity of the elliptic curve point multiplier. The architecture proves to be the fastest among all known design approaches, while complexity is less than half of that of previous efforts. This architecture also supports the required input (binary-to-RNS) and output (RNS-to-binary) conversions. Through a graph-oriented approach, the area of the elliptic curve point multiplier is minimized, by optimizing the point addition and doubling algorithms. Also, through this approach, the number of execution steps for point addition is matched to the number of execution steps for point doubling. Additionally, the impact of various RNS bases, in terms of number of moduli and their bit lengths, on the area and speed of the proposed implementation is analyzed, in an effort to define the potential for using RNS in elliptic curve cryptography. © 2009 IEEE